Transistor scaling has provided continued improvement in speed performance and circuit density in ultra-large scale integrated (ULSI) chips over the past few decades. As the gate length of the conventional bulk metal-oxide-semiconductor field-effect transistor (MOSFET) is reduced, it suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-30 nm regime, the requirements for body doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet in conventional device structures where bulk silicon substrates are employed.
A promising approach to control short-channel effects and to sustain the historical pace of scaling is to use alternative device structures such as ultra-thin body transistors and multiple-gate transistors. An ultra-thin body (UTB) transistor has a body thickness that is less than half the gate length. In an ultra-thin body transistor, all current paths between the source and drain are in close proximity to the gate, resulting in good gate control of the channel potential. Multiple-gate transistor structures include the double-gate structure, triple-gate structure, omega-FET structure, and the surround-gate or wrap-around gate structure. A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate potential of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps to suppress short channel effects, and prolongs the scalability of the MOS transistor.
In the above-mentioned nanoscale device structures (including UTB transistors and multiple-gate transistors), the high current density flowing in the devices means that series resistances are an important consideration in the optimization of device performance. In addition, variations in the series resistance in the source and drain regions of the device result in significant variations in the electrical characteristics of the device. A manufacturable process needs to have an adequate robustness to ensure that variations in the device series resistance are kept to a minimum.
For illustration purposes, an advanced device structure such as an ultra-thin body (UTB) transistor is first considered. FIG. 1A shows an enlarged, plane view of the UTB transistor 10. FIG. 1B shows an enlarged, cross-sectional view through the dashed line A–A′ of FIG. 1A. The UTB transistor 10 comprises an ultra-thin body 12 overlying an insulator layer 14 and a silicon substrate 30. A transistor with a source 16 and a drain 18 separated by a gate electrode 20 is formed on the ultra-thin body 12. The gate electrode 20 is further insulated by a spacer 32 and a gate dielectric layer 34. A silicide layer 22 is formed in the source and drain regions 16,18. Electrical connections to the source and drain regions 16,18 are formed by conductive contacts 24,26 to the silicided contact area 22. Electrical current flowing from the source contact 24 to the drain contact 26 passes from source contact 24 into the silicided contact area 22 in the source, enters the source region 16, the channel region 28 of the transistor 10, and into the drain region 18. The current then flows from the drain region 18 to the silicided contact area 22 in the drain region 18 to the drain contact 26. The current encounters resistances in various parts of the transistor 10 as mentioned above. In an actual manufacturing process, the conductive contacts 24,26 may be misaligned.
Referring now to FIG. 2, an example of a misaligned contact is illustrated. In this example, both the source and the drain contacts 24,26 are misaligned to the right. Consequently, the distance between the source contact 24 and the channel region 28 is reduced, while the distance between the drain contact 26 and the channel region 28 is increased. This results in a reduced source resistance and an increased drain resistance. Such variations in the source and drain resistances in the transistor 40 results in variations in the device characteristics.
It is therefore an object of the present invention to provide a self-aligned contact hole for nanoscale silicon-on-insulator (SOI) devices.
It is another object of the present invention to provide a method for forming nanoscale SOI devices with self-aligned source and drain contacts.